Neuromorphic computing systems typically comprise neuron and synapse circuits arranged in a massively parallel manner to support the emulation of large-scale spiking neural networks. Different approaches have been proposed for hardware implementations of neuromorphic computing systems, ranging from digital CMOS ones based on synchronous [1] and asynchronous logic [2, 3], to analog and mixed-signal ones based on standard strong inversion circuits [4] and weak-inversion circuits [5À7]. Although implemented in pure conventional CMOS technology, most of these neuromorphic architectures are optimally suited for cointegration with memristive devices, which can be used to both emulate synaptic function and to support nonvolatile local storage of network parameters [8, 9]. In such architectures, memory elements (eg, that store the synaptic state) are used also as computing elements (ie, that convert input pulses into weighted synaptic currents) and are placed just next to the main processing units (ie, the neurons that integrate all synaptic inputs and produce output spikes). These architectures are radically different from the ones based on the classical von Neumann computer one, in which memory and compute elements are implemented in separate and distinct blocks that exchange data across a common shared bus, as quickly as possible. The spiking neural networks implemented by the neuromorphic architectures can be configured to carry out multiple types of signal processing tasks, ranging from sensory signal processing [10] to pattern recognition [6], to finite-state-machine like computation [11]. These spiking neural networks …