The racetrack memory device is a new concept of Magnetic RAM (MRAM) based on controlling domain wall (DW) motion in ferromagnetic nanowires. It promises ultra-high storage density thanks to the possibility to store multiple narrow DWS per memory cell. By using read and write heads based on magnetic tunnel junctions (MTJ) with perpendicular magnetic anisotropy (PMA) fast data access speed can also be achieved. Thereby the racetrack memory can be used as universal storage to address both embedded and standalone applications. In this paper, we present the device physics, integration circuit and architecture designs of a racetrack memory based on MTJs with PMA. Mixed SPICE simulations at 65 nm node demonstrate the capabilities of this device to perform high performances. Finally, we compare the potential specifications of the racetrack memory with other advanced non-volatile memory …